A Redundant Array of Independent Disks (RAID) combines a plurality of physical hard disk drives into a logical drive for purposes of reliability, capacity, or performance. Thus, instead of multiple physical hard disk drives, an operating system sees the single logical drive. As is well known to those skilled in the art, there are many standard methods referred to as RAID levels for distributing data across the physical hard disk drives in a RAID system.
For example, in a level 0 RAID system the data is striped across a physical array of hard disk drives by breaking the data into blocks and writing each block to a separate hard disk drive. Input/Output (I/O) performance is improved by spreading the load across many hard disk drives. Although a level 0 RAID improves I/O performance, it does not provide redundancy because if one hard disk drive fails, data is lost
A level 5 RAID system provides a high level of redundancy by striping both data and parity information across at least three disk drives. Data striping is combined with parity to provide a recovery path in case of failure. A level 6 RAID system provides an even higher level of redundancy than a level 5 RAID system by enabling recovery from double disk failures.
In a level 6 RAID system, two syndromes referred to as the P syndrome and the Q syndrome are generated for the data and stored on disk drives in the RAID system. The P syndrome is generated by simply computing parity information for the data (data blocks (strips)) in a stripe (data blocks (strips), P syndrome block and Q syndrome block). The generation of the Q syndrome requires Galois Field (GF) multiplications and is a more complex computation. The regeneration scheme to recover data and/or P syndrome block and/or Q syndrome block performed during disk recovery operations requires both GF and inverse operations.
The generation and recovery of the P and Q syndrome blocks for RAID 6 and parity for RAID 5 requires the movement of large blocks of data between system memory and a storage device (I/O device). Typically, an Input Output (I/O) Controller (IOC) in a computer system includes a Direct Memory Access (DMA) controller (engine) to perform transfers of data between memory and the I/O device. The computer system can also include a DMA controller used for memory to memory data transfers. A DMA controller allows a computer system to access memory independently of the processor (core). The processor initiates a transfer of data from a source (memory or I/O device (controller)) to a destination (memory or I/O device (controller)) by issuing a data transfer request to the DMA controller. The DMA controller performs the transfer while the processor performs other tasks. The DMA controller notifies the processor, for example, through an interrupt when the transfer is complete. Typically, a DMA controller manages a plurality of independent DMA channels, each of which can concurrently perform one or more data transfers between a source and a destination.
Typically, a data transfer from a source to a destination is specified through the use of a descriptor, that is, a data structure stored in memory that stores variables that define the DMA data transfer. For example, the variables can include a source address (where the data to be transferred is stored in the source (memory (or I/O device)); size (how much data to transfer) and a destination address (where the transferred data is to be stored in the destination (memory (or I/O device)). The use of descriptors instead of having the processor write the variables directly to registers in the DMA controller prior to each DMA data transfer operation allows chaining of multiple DMA requests using a chain of descriptors. The chain of descriptors allows the DMA controller to automatically set up and start another DMA data transfer defined by a next descriptor in the chain of descriptors after the current DMA data transfer is complete.
Although the following Detailed Description will proceed with reference being made to illustrative embodiments of the claimed subject matter, many alternatives, modifications, and variations thereof will be apparent to those skilled in the art. Accordingly, it is intended that the claimed subject matter be viewed broadly, and be defined only as set forth in the accompanying claims.